1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit using a synchronized control signal.
2. Description of the Related Art
Recently, the operation speeds of semiconductor integrated circuits have increased, and the circuit scale thereof has become large. Further, it has become necessary to supply a synchronized signal (phase synchronized clock signal) to a specific circuit in a large scale semiconductor integrated circuit.
Concretely, for example, the operation speeds of memory devices, e.g., synchronous DRAMs (SDRAMs), now exceeds 100 MHz, and a DLL (Delay Locked Loop) circuit has been used to synchronize a signal with an external clock and supply the synchronized signal to a plurality of output buffers, so as to remove a delay in an internal clock. Namely, the phase of the external clock is coincident with that of the internal clock, and thereby a delay or fluctuation of an access time is removed.
By the way, when an operation speed of the SDRAM is extremely increased and a period (clock cycle) of the external clock is shortened, the delay of the internal clock is longer than one clock cycle of the external clock. Namely, a synchronous internal clock cannot be generated by synchronizing with the timing of preceding one clock cycle of the external clock.
Further, when a phase comparison operation for synchronizing the internal clock with the external clock is carried out at a respective timing (each one clock cycle) of the external clock, the internal clock signal is slightly changed and is not preferable.
The related arts and their associated problems will be described, later, with reference to the accompanying drawings.